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Junyi Xie

  • Email: Must_Login
  • Registered on: 10/23/2017
  • Last connection: 04/12/2019

Issues

Activity

04/15/2019

02:26 PM Verilator Issue #1418: Having trouble assigning signals of interfaces to regs within for loop
Hi Wilson,
We come across a Xilinx page that suggests having for loop inside always_comb helps to save runtime.
h...

04/12/2019

08:54 PM Verilator Issue #1418: Having trouble assigning signals of interfaces to regs within for loop
This is reasonable.
Thanks for the quick reply by the way!
06:50 PM Verilator Issue #1418 (WillNotFix): Having trouble assigning signals of interfaces to regs within for loop
Hi Wilson,
I experienced errors when I tried to assign signals of an interfaces array to 2-d regs.
Attached are e...

11/06/2017

02:46 PM Verilator Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
Thanks Wilson! I will have a try on the new feature.
Junyi

10/26/2017

05:03 PM Verilator Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
And probably make it opt-in / opt-out so user can do the performance-safety tradeoff
05:02 PM Verilator Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
3 can be good. We should not let over-width inputs still pass to input port. If this happens, maybe throwing an excep...

10/23/2017

10:39 PM Verilator Issue #1238 (Closed): Verilator concatenation error when passing overflowed value from C++ to ver...
Hi Verilator team,
I have found something related to memory accessing in Verilator.
When the value from C++ inp...

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