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Christopher Russell

  • Email: Must_Login
  • Registered on: 12/27/2017
  • Last connection: 08/04/2019

Issues

Activity

08/08/2019

10:31 PM Verilator Issue #1276: vcd trace splits packed data type when it comes through a typedef
I'll try to pull the latest version and see what happens. It's been a while since I updated verilator. I'll update ...

08/04/2019

03:32 PM Verilator Issue #1276: vcd trace splits packed data type when it comes through a typedef
Sorry for the extremely delayed response. This is still affecting VCD output. I think I've distilled it to a much s...

02/13/2018

07:59 PM Verilator Issue #1276 (NotEnoughInfo): vcd trace splits packed data type when it comes through a typedef
In our verilog code, we have something similar to the below typedef:...
07:50 PM Verilator Issue #1275: genvar in always_comb doesn't fail or lint warn during compile when not in a generat...
I might look into it after I get some downtime at work. I'll reference the original issue for what you may have alre...

02/11/2018

11:53 PM Verilator Issue #1275 (Duplicate): genvar in always_comb doesn't fail or lint warn during compile when not ...
I think the language spec only allows for genvar variable usage in always_comb and assign when under a generate scope...

12/27/2017

07:28 PM Verilator Usage: verilator unpacked dimension signal dependency without circular logic error
After reviewing the similarity of my issue to the issue here:
https://www.veripool.org/issues/739-Verilator-Multidim...

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