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Steven Milburn

  • Email: Must_Login
  • Registered on: 02/14/2018
  • Last connection: 02/14/2018

Issues

Activity

02/14/2018

05:48 AM Verilator Issue #1277 (WillNotFix): instantiate SystemC model in Verilog dut
Hello,
I'm trying to verilate a system with the following hierarchy:
sim_main.cpp as a testbench instantiating ...

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