General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Abdullah Raza Khan

  • Email: Must_Login
  • Registered on: 02/20/2018
  • Last connection: 02/20/2018

Issues

Activity

02/20/2018

02:18 PM Verilator Usage: Building emulator using verilator
I know we can create the c++ model of hardware in verilator. If I have generated the obj_dir after passing the small_...

Also available in: Atom