- Email: Must_Login
- Registered on: 03/05/2018
- Last connection: 08/30/2018
- 11:16 AM Verilator Issue #1327: Strange initialisation behaviour with "VinpClk" cloned clock variables
- Hi there,
Sorry for the slow reply. I've written a silly test that shows this. I suspect it's a little flaky (beca...
- 01:32 PM Verilator Issue #1327 (Closed): Strange initialisation behaviour with "VinpClk" cloned clock variables
- We're seeing a strange behaviour in our system testbench. I've tracked
it down to a problem with (seemingly) spuriou...
- 10:49 AM Verilator Issue #1309 (Closed): Mismatched new  / delete 
- In verilated_vcd_c.cpp, there is a deletion of "m_wrBufp" without "". This probably doesn't cause any actual proble...
- 07:32 AM Verilog-mode Issue #1283: Feature request: Allow user to break movement on '_' symbols
- Ok, I can do that. Do I need FSF papers on file? (I have from my past employer, but have actually moved jobs since th...
- 01:33 PM Verilog-mode Issue #1283 (Confirmed): Feature request: Allow user to break movement on '_' symbols
- The default behaviour of verilog-mode is that '_' is a word constituent (syntax class 'w'). This means that M-f and M...
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