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Peter Gerst

  • Email: Must_Login
  • Registered on: 06/19/2018
  • Last connection: 12/02/2019

Issues

Activity

11/27/2019

02:07 PM Verilator Issue #1369: Raise error / warning on continous assignment to reg
Warning about assigning to output reg does not work for me. I'm using tag 4.022 without success....

06/17/2019

10:11 AM Verilator Issue #1462: signal redeclaration is not reported
I tried the first example with version 4.016 but it did not worked. Verilator did not raise warning or error on dupli...

06/12/2019

01:38 PM Verilator Issue #1462 (Closed): signal redeclaration is not reported
I am using verilator to lint verilog modules which will be then synthesized by Xilinx tools. Prior to synthesis veril...

05/09/2019

07:03 AM Verilator Issue #1424: Verilator does not complain about invalid parameter declaration
It works. Thank you very much!

04/30/2019

12:43 PM Verilator Issue #1424: Verilator does not complain about invalid parameter declaration
Sounds perfect. Thank you!
11:15 AM Verilator Issue #1424: Verilator does not complain about invalid parameter declaration
From the referenced documentation it seems to me that initial value can be omitted only in exceptional cases, but I m...
09:51 AM Verilator Issue #1424 (Closed): Verilator does not complain about invalid parameter declaration
Verilator fails to trow syntax error on parameter declaration without constant expression, like this:...

12/04/2018

06:46 AM Verilator Issue #1369: Raise error / warning on continous assignment to reg
Thank you for the fix! verilator now raises error on _internal_reg_ but does not recognize the case of _out_ signal i...

11/30/2018

06:50 AM Verilator Issue #1369: Raise error / warning on continous assignment to reg
Xilinx ISE 14.7 syntheser complains about this:...

11/29/2018

08:59 AM Verilator Development: RE: Verilator fails to warn/error on procedural assignment to wire
Thank you for the fix! It works fine for procedural assignment on wire. I submitted an issue about continuous assignm...

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