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Yu Sheng Lin

  • Email: Must_Login
  • Registered on: 08/12/2018
  • Last connection: 04/16/2019

Issues

Activity

04/16/2019

02:51 AM Verilator Development: RE: Error on indexing the multiple dimensional array (MDA)
Disabling this branch in V3Unknown.cpp temporarily resolves the problem.
While the comments say that it slows down s...

04/11/2019

05:58 AM Verilator Development: RE: Error on indexing the multiple dimensional array (MDA)
Also, sometimes the error message is...

04/08/2019

02:52 AM Verilator Development: Error on indexing the multiple dimensional array (MDA)
I am using v4.012 and find a problem on slicing MDA non-power-of-2 array with variables.
In the following example, i...

04/07/2019

02:53 PM Verilator Installation: RE: [Installation Error in Windows 10 OS]: Facing an error related to Bison.
Since you are using Windows 10, Windows Subsystem for Linux (WSL) should work for you.

03/03/2019

07:59 AM Verilator Usage: RE: Multiple comma-separated declaration in one for-loop
I add 2 small files for this and this regression works fine. Also, t_for_comma_bad regression can be removed later.
...

02/23/2019

12:49 PM Verilator Usage: RE: Multiple comma-separated declaration in one for-loop
I implement the basic version for this feature based on v4.008.
Current code is changed significantly since later as...

02/12/2019

04:50 PM Verilator Development: Environment variable VERILATOR_GDB is not used.
Hello, I find that the Environment variable VERILATOR_GDB is not respected when launching Verilator.
According to th...

01/19/2019

10:15 AM Verilator Usage: RE: Multiple comma-separated declaration in one for-loop
Hello, I find supporting this is difficult since I have little experience about compilers.
I try to work on this but...

12/20/2018

09:25 AM Verilator Issue #1238: Verilator concatenation error when passing overflowed value from C++ to verilog inpu...
I also bump into this problem, so I reply to this closed issue.
This problem is somewhat common and hard to identify...

10/17/2018

01:02 PM Verilator Usage: Multiple comma-separated declaration in one for-loop
Hello.
In the SystemVerilog standard,
there can be multiple comma-separated in one for-loop declaration like this...

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