- Email: Must_Login
- Registered on: 09/07/2018
- Last connection: 09/07/2018
- 05:59 PM Verilator Development: RE: A problem with shared Vlvbound variables
- > The vlbound's don't really have any usefulness related to visualizing, I'd ignore them or have a flag to not create...
- I've been working on a tool that uses Verilator to produce a netlist graph from the AST of a Verilog design. I've bas...
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