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Xusine Lin

  • Email: Must_Login
  • Registered on: 03/14/2019
  • Last connection: 03/28/2020

Issues

Activity

03/15/2019

11:12 AM Verilator Issue #1409: Incorrect Result of Cascading Module Using Generate Statement
Thanks! It works!

03/14/2019

01:28 PM Verilator Issue #1409: Incorrect Result of Cascading Module Using Generate Statement
In spite of the disorder I packed my code into the attachment.
01:23 PM Verilator Issue #1409 (NoFixNeeded): Incorrect Result of Cascading Module Using Generate Statement
Hi. I use Verilator to verify a ripple carry adder formed by a series of full adders generated by generate statement ...

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