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Paul Donahue

  • Email: Must_Login
  • Registered on: 06/05/2019
  • Last connection: 11/12/2019

Issues

Activity

11/13/2019

09:39 PM Verilator Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
I'm not sure if you mean that the warning can be disabled for my case or the fundamental issue can be fixed for my ca...

11/12/2019

10:17 PM Verilator Issue #364: blocking & non-blocking assigns -- verilator issues error when no logical conflict ex...
I am running into this problem very frequently with RTL that extensively uses packed structs. For instance this does...

07/26/2019

12:14 AM Verilator Issue #1482 (Feature): Conditional event controls ("iff")
Section 9.4.2.3 of IEEE 1800-2017 allows "iff" qualifiers on @ event controls. The example code in 9.4.2.3 is fairly...

06/14/2019

10:04 PM Verilog-mode Issue #1466 (Closed): Documentation bugs
I think that there are a few related bugs in the documentation. It all seems to have to do with the port names on In...

06/12/2019

12:49 AM Verilog-mode Issue #1461: Structs as output ports don't work with stub generation recipe
Thanks for another fast response. I'm sorry to bother you since I see now that this is already documented.
Your s...

06/11/2019

08:57 PM Verilog-mode Issue #1461 (NoFixNeeded): Structs as output ports don't work with stub generation recipe
I have this port list on a module:...

06/10/2019

11:56 PM Verilog-mode Issue #1457: endclocking not indented properly on default clocking blocks
Looks good. Thanks for the quick response.

06/05/2019

09:48 PM Verilog-mode Issue #1457: endclocking not indented properly on default clocking blocks
That didn't look good at all. I misunderstood the user interface on preview vs. create. Here's the original descrip...
09:43 PM Verilog-mode Issue #1457 (Closed): endclocking not indented properly on default clocking blocks
Clocking blocks seem to indent appropriately with verilog-batch-indent but default clocking blocks (IEEE 1800-2017 se...

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