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- Registered on: 06/10/2019
- Last connection: 06/10/2019
- 09:32 AM Verilog-Perl Issue #1463 (WillNotFix): Vhier : Usage to display whole hierarchy of a pin or a port in a module...
- Suppose I have a verilog file with modules and lots of sub modules and also with pins inside the submodule.
I want t...
- 08:06 AM Verilog-Perl Using: RE: Names
- Yes , it is
- 05:30 AM Verilog-Perl Using: RE: Verilog::Regex
- Which parser may i know?
- Is there a Regex file where there are patterns for pins and modules. I want to know how does this module knows that t...
- 04:26 AM Verilog-Perl Using: RE: Names
- I will explain you clearly now. The errors or the fault points generated through formality in 2 verilog files , I wan...
- 11:50 AM Verilog-Perl Issue #1459: Getting Error with Verilog::Netlist Module
- ok sir , I will explore this package , I am exploring the Netlist folder quite a while , do i have to explore other t...
- 11:48 AM Verilog-Perl Using: RE: Names
- The error generated through formality cant be corrected with the help of this?
- 11:39 AM Verilog-Perl Issue #1459: Getting Error with Verilog::Netlist Module
- Like these are available in the standard verilog libraries, Can't I import them?
or Do I have to make this kind of ....
- 11:36 AM Verilog-Perl Using: RE: Names
- i was thinking to store contents of one in array1 and other in array 2 and compare them .. you have a better option a...
- 11:35 AM Verilog-Perl Using: RE: Names
- I want to compare 2 verilog files and find error in them and display them
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