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Slava B

  • Email: Must_Login
  • Registered on: 07/29/2019
  • Last connection: 09/11/2019

Issues

Activity

09/11/2019

12:55 PM Verilator Usage: RE: any chance of gettting deassign working?
Any news related to the substitution story mentioned by Wilson? I cannot verilate a project due to usage of deassign ...

09/09/2019

10:40 AM Verilator Usage: RE: Conversion of a hierarchical design
By the way, sw debugging became less relevant when I found out that it is possible to add internal Verilog signals to...
10:19 AM Verilator Usage: Single-bit signals represented as VL_SIG8
Hi,
I was curious why single-bit signals are represented in verilated SystemC code as:
...

09/04/2019

01:48 PM Verilator Usage: RE: Conversion of a hierarchical design
I understand your point. If the compiled design and test-bench start working properly from the fist moment, everythin...
11:51 AM Verilator Usage: Conversion of a hierarchical design
Hi,
First of all, thanks for the great tool. I took a big design, written in Verilog, and converted it to SystemC ...

09/03/2019

01:30 PM Verilator Usage: RE: Verilator should have converted inout ports to input/output pairs.
Thanks for explanations!
08:27 AM Verilator Usage: Verilator should have converted inout ports to input/output pairs.
Hi,
As far as I understand from the documentation, Verilator should convert inout ports to input/output pairs. Is ...
07:47 AM Verilator Development: RE: sc_inout and tristate support
Hi,
Is there any update on this very important feature?
Regards,
Slava

08/27/2019

08:13 AM Verilator Usage: Unsupported: wor
Hello,
I'm trying to convert a big project and receive the following message: *Unsupported: wor*. As far as I unde...

08/07/2019

05:18 AM Verilator Issue #1488: A strange code generated from a parametric module.
Thank you very much, Wilson! I was not aware about --pins-sc-uint switch!

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