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James Connolly

  • Email: Must_Login
  • Registered on: 08/09/2019
  • Last connection: 11/05/2019

Issues

Activity

09/12/2019

03:27 PM Verilator Usage: RE: Increasing performance in a moderately clock gated design
Thanks for the tips here Wilson; I massaged some of the arbiters to be optimized by V3Table and got great speedup wit...

08/22/2019

05:43 PM Verilator Usage: RE: Increasing performance in a moderately clock gated design
Nasty combinational logic with nested loops seems to be where I'm sinking most of my cycles (~30% of time). Attached ...

08/15/2019

06:09 PM Verilator Usage: Increasing performance in a moderately clock gated design
I've been looking at speeding up verilator for a design. A few months ago I added in a large module that is mostly id...

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