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Oleg Rodionov

  • Email: Must_Login
  • Registered on: 09/10/2019
  • Last connection: 10/28/2019

Issues

Activity

10/28/2019

03:52 AM Verilator Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
Todd, I was able to compile my core with -dpi-protect flag. I do see static library being generated, but I don't see ...

10/25/2019

05:33 AM Verilator Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
I was able to replace verilated uC core into my RTL design and simulate with VCS. I did following steps:
1. Verilat...

09/10/2019

08:09 PM Verilator Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
Todd, I downloaded the link. Verilator version doesn't have all the familiar makefiles and configuration. How do I ...
05:32 PM Verilator Usage: RE: Using vcs to simulate design with multiple verilated uC cores?
Awesome! Thank you Todd. I will check it out and report back. If it works good enough to re-run the same simulati...
02:16 PM Verilator Usage: Using vcs to simulate design with multiple verilated uC cores?
In my vcs simulation model, for certain, simulation content, I see majority of simulation time spent in the microcont...

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