General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

w z

  • Email: Must_Login
  • Registered on: 10/14/2019
  • Last connection: 10/14/2019

Issues

Activity

10/16/2019

01:37 AM Verilator Issue #1554: There is a problem when Handling variables forced type conversion
this is the test code,maybe you can use fore reference.
01:05 AM Verilator Issue #1555: Asynchronous reset logic is inconsistent with rtl
great,thanks very much for your help

10/15/2019

11:55 AM Verilator Issue #1554: There is a problem when Handling variables forced type conversion
we also use CARBON's CMS tool,the result in line with expectations, it can correctly do type conversion with width va...
08:46 AM Verilator Issue #1555 (NoFixNeeded): Asynchronous reset logic is inconsistent with rtl

hi,
On RTL, asynchronous reset does not require a falling edge to trigger the initial value.verilaror is inconsist...
08:38 AM Verilator Issue #1554 (AskedReporter): There is a problem when Handling variables forced type conversion

The result of this shift should be related to the bit width of the operation. For example, the previous operation v...

Also available in: Atom