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Aimless Ramble

  • Email: Must_Login
  • Registered on: 11/14/2019
  • Last connection: 11/17/2019

Issues

Activity

11/17/2019

06:39 PM Verilator Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of...

11/16/2019

07:25 PM Verilator Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> >But it doesn't capture internal behavioral source/destination
>
> It does, for example s...

11/15/2019

08:41 PM Verilator Issue #1599: A Signal Connectivity Parser Within a Verilog Module
Wilson Snyder wrote:
> Verilog-perl has some of this information, but from what you describe I would suggest first l...

11/14/2019

06:40 PM Verilator Issue #1599 (NoFixNeeded): A Signal Connectivity Parser Within a Verilog Module
I have trying to form a signal connectivity Parser within a Module file. It Can read (one or multiple) Verilog files ...

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