Veripool

12/10/2016

08:08 PM Verilator Usage: RE: Can you force evaluation of a signal every tick

That seems to be working...
Thanks.

05:59 PM Verilator Usage: Can you force evaluation of a signal every tick

I have a PLL model that uses `system_c to create a C++ object that then uses the global main_time variable to synthes...

10/09/2014

03:17 PM Verilator Issue #826: /*verilator tracing_off*/ causes compile errors

Wilson,
Is there any other way to disable tracing only on a certain branch of the hierarchy?

09/30/2014

08:16 PM Verilator Issue #826 (Closed): /*verilator tracing_off*/ causes compile errors

We are embedding a Xilinx microblaze processor into an FPGA. I want tracing for it and all its dependencies disabled ...

02/14/2014

04:18 PM Verilator Issue #716 (Closed): Crash with port = syntax error

I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Fol...

07/08/2011

04:30 PM Verilator Development: RE: Bidirectional arrayed ports

Chandan,
While it is in the plans to support bidirectional arrayed ports, it is not currently scheduled. Sorry.

03/24/2010

07:36 PM Verilator Issue #226: Improve error handling on slices of packed arrays

I did a little more digging into this problem, and it seems like a false alarm. I checked out the main branch without...

08:46 AM Verilator Issue #226: Improve error handling on slices of packed arrays

Previously I mentioned that even after reverting this patch that I was still having problems. That was not correct. S...

07/02/2009

05:21 AM SystemPerl Issue #100 (Closed): uint32_t undefined in SpCommon.h

I am using the new verilator and system perl v1.321 rpms for Fedora and ran into the following error when compiling w...

05/08/2009

05:44 PM Verilator Usage: Specifying verilator options externally

I have a synthesized netlist. Is there a way, other than through inline verilog comments, to set options such as 'pu...