- Email: Must_Login
- Registered on: 07/09/2008
- Last connection: 12/10/2016
- Verilator (Developer, 01/22/2009)
- 08:08 PM Verilator Usage: RE: Can you force evaluation of a signal every tick
- That seems to be working...
- I have a PLL model that uses `system_c to create a C++ object that then uses the global main_time variable to synthes...
- 03:17 PM Verilator Issue #826: /*verilator tracing_off*/ causes compile errors
Is there any other way to disable tracing only on a certain branch of the hierarchy?
- 08:16 PM Verilator Issue #826 (Closed): /*verilator tracing_off*/ causes compile errors
- We are embedding a Xilinx microblaze processor into an FPGA. I want tracing for it and all its dependencies disabled ...
- 04:18 PM Verilator Issue #716 (Closed): Crash with port = syntax error
- I discovered that adding an '=' symbol to a verilog port causes verilator_bin to %Error without a useful message. Fol...
- 04:30 PM Verilator Development: RE: Bidirectional arrayed ports
While it is in the plans to support bidirectional arrayed ports, it is not currently scheduled. Sorry.
- 07:36 PM Verilator Issue #226: Improve error handling on slices of packed arrays
- I did a little more digging into this problem, and it seems like a false alarm. I checked out the main branch without...
- 08:46 AM Verilator Issue #226: Improve error handling on slices of packed arrays
- Previously I mentioned that even after reverting this patch that I was still having problems. That was not correct. S...
- 05:21 AM SystemPerl Issue #100 (Closed): uint32_t undefined in SpCommon.h
- I am using the new verilator and system perl v1.321 rpms for Fedora and ran into the following error when compiling w...
- I have a synthesized netlist. Is there a way, other than through inline verilog comments, to set options such as 'pu...
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