General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  BugVise
  CovVise
  Force-Gate-Sim
  Gspice
  IPC::Locker
  Rsvn
  SVN::S4
  Voneline
  WFH
General Info
  Papers

Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 03/27/2017

Issues

Projects

Activity

03/27/2017

07:49 PM Verilator Usage: RE: can I ‘--trace’ the signals in the sub-module which I specify only, NOT the top module...
Put test.vlt on the command line. The vlt files only support the commands shown in the manual, but we welcome a cont...
03:55 PM Verilator Issue #1148 (NoFixNeeded): Verilator not handling individual generate/if blocks.
02:24 AM Verilator Usage: RE: can I ‘--trace’ the signals in the sub-module which I specify only, NOT the top module...
See the manual, Verilator supports configuration files.

03/24/2017

03:15 PM Verilator Usage: RE: Related to BLKANDNBLK error while linting
Same as disabling a warning.
// verilator lint_off BLKANDNBLK
...
// verilator lint_on BLKANDNBLK
or se...
11:32 AM Verilator Usage: RE: Related to BLKANDNBLK error while linting
You need to rewrite the code, or turn off the warning (see the verilator manual) which will risk getting the wrong si...
11:30 AM Verilator Usage: RE: unique case linting
See the SystemVerilog manual - unique doesn't insure coverage. So verilator is warning you you don't have it.
And...
11:28 AM Verilator Usage: RE: can I ‘--trace’ the signals in the sub-module which I specify only, NOT the top module...
There is no way to do this at present with --trace. Dump to a local flash disk, and only a small bracket of time.
...

03/23/2017

10:17 PM Verilator Issue #1009: Non-cutable ordering loop when using an array of clocks
>if we have V3Gate look for concatenated clockers and stash that information in the ASSIGNW nodes, then we can push t...
10:16 PM Verilator Issue #1145 (Resolved): Assigning to the same member twice in struct named assignment does not re...
10:15 PM Verilator Issue #1145: Assigning to the same member twice in struct named assignment does not result in an ...
Great, thanks for the test too.
Pushed to git towards 3.902.

Also available in: Atom