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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 04/17/2019

Issues

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Activity

04/17/2019

11:56 PM Verilator Issue #1305: Error messages do not contain hierarchical information
Nodes don't exist in the lexer. I suppose we cold make fake temp nodes, but don't like this as some alternative futur...

04/13/2019

04:01 PM Verilator Usage: RE: eval() multiple times on same clock edge
Perhaps declare a DPI import function. Then create an always sensitivity list (real or fake) and Verilator will then...

04/12/2019

08:35 PM Verilator Issue #1418 (WillNotFix): Having trouble assigning signals of interfaces to regs within for loop
Verilator currently requires interface (or cell) references must be statically unrolled. This is currently a fairly f...
05:19 PM Verilator Issue #1305: Error messages do not contain hierarchical information
V3Number started long ago as a relatively independent thing without concept of nodes, but don't see a reason it has t...

04/11/2019

12:52 AM Verilator Issue #1417 (Resolved): FST regression tests fail instead of skip if fst2vcd isn't installed
Fixed in git towards 4.014.

04/10/2019

01:34 AM Verilog-Perl Verilog-Perl 3.462 Released
Verilog::Language 3.462 2019-04-09
*** Fix legacy $pin->netlist accessor.
*** Fix nettype declarations,...

04/09/2019

08:23 PM Verilog-mode Issue #1416 (NoFixNeeded): problems getting Verilog-batch-auto to work with library file
Good to hear.
08:05 PM Verilog-mode Issue #1416 (AskedReporter): problems getting Verilog-batch-auto to work with library file
-l path/to/verilog-mode.el
07:32 PM Verilog-mode Issue #1416: problems getting Verilog-batch-auto to work with library file
I would suggest adding an appropriate debug message near line 10130 where that error is printed to also print verilog...
01:31 AM Verilator Development: RE: Error on indexing the multiple dimensional array (MDA)
As you noted this is an error, but the message is confusing because the out-of-bounds gets converted to a constant be...

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