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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 11/19/2019

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Today

03:11 AM Verilator Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
03:06 AM Verilator Usage: RE: Basic questions: Multiple modules and using "#"
1) Yes, you can put multiple modules per file.
2) You'd write this in C code, for example in = 0; then make time p...

11/18/2019

10:04 AM Verilator Issue #1607 (Closed): CI: Add gtkwave include diff to extended tests
A pull is out against GTKwave. Once this completes:
- Move personal script to compare GTKwave include upstream to ...

11/17/2019

09:58 AM Verilator Issue #1606 (Feature): Complete string methods (starter project)
Implement the built-in string methods that are remaining:
- atobin, atohex, atoi, atooct, atoreal: Become a scanf....

11/16/2019

10:24 PM Verilator Issue #1604 (Resolved): Unknown node in split color() map on empty if
Thanks for the good test case.
This was caused by your outputs (rx & ry) never being used, not sure if you noticed...
08:18 PM Verilator Issue #1599: A Signal Connectivity Parser Within a Verilog Module
All the bits are used, unless there is a "sel" (select) operation which pulls off a subset of the bits that are speci...
07:11 PM Verilog-Perl Issue #1546 (NotEnoughInfo): perl 'make' commandline error during installation
Assume this got figured out.

11/15/2019

11:38 PM Verilator Issue #1604 (Confirmed): Unknown node in split color() map on empty if
Will require some research. The irony is the point of the broken optimization is to transform it into exactly what y...
11:25 PM Verilator Issue #1605 (Resolved): for loop initialisation clause skipped
Sorry, that's nasty and should have been caught earlier, so fixing immediately.
FWIW "for (i=1; 0; )" was tested, ...
08:48 PM Verilator Issue #1599: A Signal Connectivity Parser Within a Verilog Module
>But it doesn't capture internal behavioral source/destination
It does, for example see the varref (references to...

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