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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 03/23/2019

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Today

01:15 AM Verilator Issue #1383 (Closed): Support SystemVerilog void casts & warn if not present
In 4.012.
01:15 AM Verilator Issue #1384 (Closed): File-extension language option not consistently applied
In 4.012.
01:15 AM Verilator Issue #1396 (Closed): Verilator random number generated seeded with lrand48(), which isn't determ...
In 4.012.
01:15 AM Verilator Issue #1400 (Closed): Bug: verilator sometimes fails to detect electrical short
In 4.012.
01:15 AM Verilator Issue #1406 (Closed): Mixed _WIN32/WIN32 definitions causes compiler error over mkdir defintion i...
In 4.012.
01:15 AM Verilator Verilator 4.012 Released
Verilator 4.012 2019-3-23
*** Add +verilator+seed, bug1396. [Stan Sokorac]
*** Support $fread. [Leendert v...

03/23/2019

11:29 AM Verilog-mode Issue #1410 (NoFixNeeded): multiple instantiations of a module
The */ you are trying to insert is taken to end the AUTO, split it. Also avoid calling the shell to make it faster a...

03/22/2019

12:59 PM Verilog-mode Using AUTOs: RE: wrong indentation with 'ref self-defined-class-name port-name' in systemverilog ...
This seems a bug in verilog-pretty-declarations. Will take a look.

03/21/2019

11:21 AM Verilog-mode Using AUTOs: RE: Verilog Wrapper for a VHDL Entity
Write them yourself.
11:20 AM Verilator Issue #1402: Compile verilator to webassembly
>But you also need to apt-get install libfl-dev (https://packages.ubuntu.com/bionic/amd64/libfl-dev/filelist).
Ubu...

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