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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 11/17/2018

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Today

11:23 AM Verilator Usage: RE: threaded compile error message
That's small, about 5K instructions in the main loop. This suggests you might be getting around 1M cycles/second (mi...

11/15/2018

11:47 PM Verilator Usage: RE: threaded compile error message
It isn't associated with an exact file so the inline pragma won't work. However we have several self tests that check...
09:36 PM Verilator Usage: RE: threaded compile error message
What's the instruction count total last column? Guessing this is a fairly small design? Small designs are unlikely ...

11/14/2018

11:56 PM Verilator Usage: RE: threaded compile error message
Roughly yes. It tries to look for many parallel tasks (many per thread). It can't find enough, but you may still if ...
11:28 AM Verilog-mode Using AUTOs: RE: Replacing the defines with the actual values
Needed to do some experiments to recall how this works. The replacements occur only in instantiating modules at the i...

11/12/2018

03:21 AM Veripool Veripool Software Update
The Veripool website software was upgraded today. If you see any strange behavior, please post an issue.

11/10/2018

01:38 PM Verilog-mode Using AUTOs: RE: Replacing the defines with the actual values
If you have `defines in a include file then do this in the parent file
// Local Variables:
// verilog-auto-read...

11/07/2018

06:42 PM Verilator Issue #1365 (Duplicate): False BLKANDNBLK error for different signals in a vector
Please see bug364.
I understand this is annoying, but is a fairly high effort limitation to resolve so hasn't been...

11/01/2018

11:53 PM Verilator Usage: RE: Getting a list of module and SystemVerilog interface dependencies
Well done, pushed to git towards 4.008.
11:04 PM Verilator Issue #1364 (Resolved): Verilator hangs in malloc() when assignment pattern key is not found
Thanks for the report. Fixed in git towards 4.008.

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