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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 10/20/2019





06:52 PM Verilator Issue #1571 (NoFixNeeded): Memory definition triggers the error "Signal unoptimizable: Feedback t...
The problem isn't that line per-se, but rather the places where it's used. In the case you provided this is a behavi...
01:21 PM Verilator Issue #1570 (Confirmed): Verilog 2001: verilator does not issue a warning on missing 'reg', Webpa...
Yes, it should warn, will look into it.
12:00 PM Verilator Issue #1569 (WillNotFix): $monitor statement isn't supported
Thanks for your report.
At this time Verilator doesn't have a time wheel, so doesn't really have a way to properly...


12:23 PM Verilator Issue #1489: Python support for Verilated designs
Review comments:
+++ b/bin/verilator
+=item --python
+This generates a file wraps the toplevel mo...
11:09 AM Verilator Issue #1568 (Closed): Spelling mistakes fixes
Thanks, pushed along with a few other fixes.
Note you need only change bin/verilator as the HTML/tex/pdf is auto-g...
01:31 AM Verilator Issue #1563 (Closed): Fuzzer: Unterminated block comment gives flex scanner internal error--end o...
Thanks for the test, some user would have hit this too, likely. Fixed in git.


10:30 PM Verilator Issue #1535: Double quotes in -f option file
Thanks for the great analysis. I don't see that there's anything at all
special about numbers, they are just normal...
02:24 AM Verilog-mode Issue #1453 (Feature): AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
If you can provide some examples I'll take a look if there's some straightforward cases I can cover (gratis). Please...
12:06 AM Verilator Issue #850: Find UNUSED and UNDRIVEN components in structs
Not currently being worked on.
12:06 AM Verilator Issue #678: Missing initial positive edge when using --x-initial-edge
Not currently being worked on.

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