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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 01/16/2019

Issues

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01/16/2019

05:42 AM Verilator Issue #1391 (Resolved): Trying to cast non-static DPI export functions to (void *)
Fixed in git towards 4.010. Please give it a try.
12:24 AM Verilator Usage: RE: Several questions, re: the `--inline-mult` option.
1. An internal ast node E.g. add.
2. Right, will fix.
3. It has been used on larger designs however gcc has bee...
12:03 AM Verilator Usage: RE: Can I call out to a foreign language module, via VPI, from a Verilog submodule?
Not easily, I think you are looking for something like this:
https://www.veripool.org/boards/3/topics/2348-Verilat...

01/15/2019

11:47 PM Verilator Usage: RE: What's a good value to give the --output-split-cfuncs flag?
Maybe start with 50000, see how long it takes, and adjust to get e.g. 5 minute gcc per c++ file.

01/14/2019

11:26 AM Verilator Issue #1372: XML output insufficiently qualified
Sorry, pushed.
02:05 AM Verilator Usage: RE: Best practice for compiling top-level test bench and linking final executable, when NO...
--exe shouldn't be slowing anything down, it just adds a make rule, you can put your .cpp's on the command line and u...
01:59 AM Verilator Issue #1372: XML output insufficiently qualified
Thanks again, pushed.
01:57 AM Verilator Issue #1391 (Confirmed): Trying to cast non-static DPI export functions to (void *)
Thanks for the additional sighting, now I know the module and think that inlining is involved, with these hints I'll ...

01/12/2019

06:46 PM Verilator Usage: RE: error: 'VL_CPU_RELAX' was not declared in this scope.
It does seem inconsistent. If you delete your vrltr_out and rebuild is it OK?
02:52 PM Verilog-mode Issue #1390 (NoFixNeeded): AUTOREG generates unexpected reg declarations in some cases
Thanks for the good writeup.
You need to tell Verilog-Mode what are outputs with // Output comments....

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