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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 05/19/2018

Issues

Projects

Activity

05/19/2018

12:04 PM Verilator Issue #1303: VCD Filter Files
Note I'm currently sitting on the above mentioned patch, since it seems fairly one-user specific and something better...
11:58 AM Verilog-Perl Issue #1299 (Closed): perl-Verilog-Perl-3.448 fails on test t/35_sigparser.t
This was fixed in 3.452 on 2018-4-12 - forgot to close.
11:22 AM Verilog-mode Issue #1310 (WillNotFix): add date/time stamp to comment
I can see how you find this useful, but unless I'm missing something, existing modes don't add the date when commenti...

05/17/2018

11:09 AM Verilator Issue #1309 (Closed): Mismatched new [] / delete []
Fixed in git, thanks.

05/13/2018

08:30 PM Veripool Privacy Statement and Terms of Service
Please see the new [[Privacy Statement]] and [[Terms of Service]]. If you do not accept these new terms, please conta...

05/09/2018

10:33 PM Verilator Issue #1307 (AskedReporter): Can not dump trace with CMAKE compiled SystemC library
10:32 PM Verilator Issue #1308 (Resolved): Missing # in parameter list crashes verilator with no useful error message
Thanks for the test case; simple enough to solve.
Fixed in git towards 3.924.

05/06/2018

02:26 PM Verilator Issue #1304 (WillNotFix): Codebase: Macro to iterate over nodes of known type
For the time being I don't think we want to change this, but I appreciate your efforts to clean up and in general exp...
02:16 PM Verilator Development: RE: Using Verilator with Buck
It's not clear how what you propose would work when a user changes say design "A" to need a new include or have a new...
11:35 AM Verilator Issue #1307: Can not dump trace with CMAKE compiled SystemC library
I haven't seen this before, but suspect & hope with some appropriate printf's or debugger it will be fairly easy for ...

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