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Wilson Snyder

  • Email: Must_Login
  • Registered on: 03/14/2008
  • Last connection: 06/22/2017

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06/23/2017

03:08 PM Verilog-Perl Issue #1179: Verilog::SigParser problems with package ordering
Great!
02:31 PM Verilog-Perl Issue #1179: Verilog::SigParser problems with package ordering
It does work like Netlist. You just need the file list in the proper order, with files containing packages first, or...
02:20 PM Verilog-Perl Issue #1179 (NoFixNeeded): Verilog::SigParser problems with package ordering
The language standard requires packages be declared before they are referenced, so most likely that's resulting in th...

06/22/2017

10:39 PM Verilator Usage: RE: dump() with non-integer timestamp
Released 3.906.
10:38 PM Verilator Issue #1152 (Closed): Parameter arrays in module parameter port list
In 3.906.
10:38 PM Verilator Issue #1176 (Closed): Implicit port connection .* does not work for interfaces
In 3.906.
10:38 PM Verilator Issue #761 (Closed): Verilator uses undeclared helper function for power op > 64 bits
In 3.906.
10:37 PM Verilator Issue #1174 (Closed): Shift gives VL_SHIFTR_IIW not declared
In 3.906.
10:37 PM Verilator Issue #1172 (Closed): Incorrect result for packed array with non-zero LSB typedef
In 3.906.
10:37 PM Verilator Verilator 3.906 Released
* Verilator 3.906 2017-06-22
*** Support set_time_unit/set_time_precision in C traces, msg2261.
*** Fix ext...

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