General

Profile

[logo] 
 
Home
News
Activity
About/Contact
Major Tools
  Dinotrace
  Verilator
  Verilog-mode
  Verilog-Perl
Other Tools
  IPC::Locker
  Parallel::Forker
  Voneline
General Info
  Papers

Brad Dobbie

  • Email: Must_Login
  • Registered on: 04/15/2010
  • Last connection: 05/16/2017

Issues

Activity

05/22/2017

04:03 PM Verilog-mode Issue #1163: Module mis-indent within generate statement
Kaushal Modi wrote:
> I confirm this issue too.
>
> I never saw this issue earlier though as my coding style is a...

05/16/2017

02:24 PM Verilog-mode Issue #1163 (Confirmed): Module mis-indent within generate statement
I've encountered an indentation problem, shown below. verilog-mode-version is "2017-04-28-6b4fc78-vpo". I'm pretty ...

05/25/2016

02:19 PM Verilog-mode Issue #1061 (Closed): Using AUTOs with parameterized types
I've found some interesting use cases for parameterized types, and I could use some help from Verilog-mode to make th...

10/28/2015

06:43 PM Verilog-mode Issue #986 (WillNotFix): AUTOWIRE misdeclares multidimensional arrays
...

07/24/2013

01:32 PM SVN::S4 Issue #665 (Feature): speedup s4 update after viewspec change
A viewspec with a bunch of switched fields is kind of annoying because SVN can only switch one item per client call. ...

07/01/2013

05:33 PM Verilog-mode Issue #663 (Closed): Indentation takes forever on lines after AUTOINST (with wildcard and elisp f...
After a recent upgrade of our site's Verilog-mode version, I notice very poor indentation performance under some circ...

08/20/2012

04:06 PM SVN::S4 Issue #551 (Closed): Add option for s4 update to update the entire project checkout
It would be useful to have an option that would update the entire tree, regardless of where the command is called fro...

08/01/2012

08:50 PM Verilog-mode Issue #539: AUTOs for wrapping a module around an interface
One of the major concepts we utilize is "vertical reuse", which means that a given interface should be able to be use...

07/31/2012

06:30 PM Verilog-mode Issue #539: AUTOs for wrapping a module around an interface
Thanks for the detailed reply, Cliff. Let me take your suggestions back to the verification team and see what they s...
06:08 PM Verilog-mode Issue #540 (Closed): AUTOINSTing an interface create illegal code
I'm not sure if this was intended behavior, but when AUTOINSTing an interface illegal code is generated.
Given an ...

Also available in: Atom