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Chandan Egbert

  • Email: Must_Login
  • Registered on: 05/06/2011
  • Last connection: 04/14/2014

Issues

Activity

04/17/2014

01:49 AM Verilator Issue #743 (Closed): "assert" under "if" with no begin/end causes internal error
The code below causes Verilator to fail with the error message...

10/18/2012

02:43 AM Verilator Issue #569 (Closed): Name of task input or output cannot be "v"
The following code does not compile....

10/16/2012

11:57 PM Verilator Issue #567: Name collision of unnamed blocks
I tried fixing the problem. Not sure if my fix is 100% correct, but here is a patch to V3LinkDot.cpp that seems to work.

10/13/2012

02:18 AM Verilator Issue #567 (Closed): Name collision of unnamed blocks
This code...

07/20/2012

02:56 PM Verilator Issue #533: Missing width warning when part of a bus is compared
If a = 16'hffff, a[5:0] would be 6'h3f. Inverting this should give 0. comparing this with 0 should give TRUE. However...
02:43 AM Verilator Issue #533 (Feature): Missing width warning when part of a bus is compared
Verilator generates incorrect code for the comparison...

11/29/2011

01:54 AM Verilator Issue #423 (Closed): DPI problem with > 32 bit but <= 64 bit args
Verilator 3.830 generates code that causes a C++ syntax error. The following verilog code...

10/01/2011

02:16 AM Verilator Issue #395 (Closed): Tristate pins again
I have a module that looks like this:...

09/21/2011

11:30 PM Verilator Issue #393: %Error: Internal Error: ...: ../V3AstNodes.h:453: Unexpected Call
To clarify, the RTL bug is that the signal "foo" in module "top" in the test case should be arrayed but is not.

09/20/2011

10:09 PM Verilator Usage: Bidirectional port slice problem
I'm running into a problem connecting bidirectional pins to slices of a bus. The following code shows the problem:
...

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