Veripool

09/11/2018

01:57 PM Verilator Issue #1342 (NoFixNeeded): False(?) UNOPT warning in combinational generate loop operating on MDA

The attached test-code generates @UNOPT@ warnings with Verilator 3.926. This is a distilled test-case that exposes a...

08/28/2018

01:52 PM Verilog-mode Issue #1335: Declaration prefixed with rand keyword is not prettified.

There's no reason that I know of to exclude 'rand' from prettifying operations. I think this was just oversight. I'...

03/26/2018

08:48 PM Verilog-mode Issue #955: End mis-indents with sized replication

Yeah, I see this too. Unfortunately, I'm not in a great place to dig in to this (again) in the near term, due to loo...

11/13/2017

09:00 PM Verilog-mode Issue #1237 (Closed): "end" not indented correctly after replication with variable number

08:59 PM Verilog-mode Issue #1237 (Resolved): "end" not indented correctly after replication with variable number

This commit fixes the test-case....

08/25/2016

04:39 PM Verilog-mode Issue #1082: Smart indenting multi-line `define

Wilson Snyder wrote:
> >Is not trying to indent the lines ending in \\$ at all a viable 'solution'?
>
> A reasona...

03/17/2016

05:05 PM Verilog-mode Issue #1047: indention after 'interface class ... endclass' is one level too deep

...

05:05 PM Verilog-mode Issue #1048 (Confirmed): indention after 'package ... endpackage' is one level too deep

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05:03 PM Verilog-mode Issue #1047 (Confirmed): indention after 'interface class ... endclass' is one level too deep

interface class ic;
...
endclass
// this should indent to left margin, but indents one stop to right

02/19/2016

07:32 PM Verilog-mode Issue #956: Using ':' for end-lable instread of "// SysteVerilog

From Kaushal Modi in www.veripool.org/issues/1038-Verilog-mode-Support-for-named-ends-Example-endclass-CLASSNAME-
...