- Email: Must_Login
- Registered on: 08/03/2011
- Last connection: 09/11/2018
- Verilog-mode (Manager, 11/06/2014)
- 01:57 PM Verilator Issue #1342 (NoFixNeeded): False(?) UNOPT warning in combinational generate loop operating on MDA
- The attached test-code generates @UNOPT@ warnings with Verilator 3.926. This is a distilled test-case that exposes a...
- 01:52 PM Verilog-mode Issue #1335: Declaration prefixed with rand keyword is not prettified.
- There's no reason that I know of to exclude 'rand' from prettifying operations. I think this was just oversight. I'...
- 08:48 PM Verilog-mode Issue #955: End mis-indents with sized replication
- Yeah, I see this too. Unfortunately, I'm not in a great place to dig in to this (again) in the near term, due to loo...
- 09:00 PM Verilog-mode Issue #1237 (Closed): "end" not indented correctly after replication with variable number
- 08:59 PM Verilog-mode Issue #1237 (Resolved): "end" not indented correctly after replication with variable number
- This commit fixes the test-case....
- 04:39 PM Verilog-mode Issue #1082: Smart indenting multi-line `define
- Wilson Snyder wrote:
> >Is not trying to indent the lines ending in \\$ at all a viable 'solution'?
> A reasona...
- 05:05 PM Verilog-mode Issue #1047: indention after 'interface class ... endclass' is one level too deep
- 05:05 PM Verilog-mode Issue #1048 (Confirmed): indention after 'package ... endpackage' is one level too deep
- 05:03 PM Verilog-mode Issue #1047 (Confirmed): indention after 'interface class ... endclass' is one level too deep
interface class ic;
// this should indent to left margin, but indents one stop to right
- 07:32 PM Verilog-mode Issue #956: Using ':' for end-lable instread of "// SysteVerilog
- From Kaushal Modi in www.veripool.org/issues/1038-Verilog-mode-Support-for-named-ends-Example-endclass-CLASSNAME-
Also available in: Atom