- Email: Must_Login
- Registered on: 02/09/2012
- Last connection: 03/27/2015
Are any plans to add the verilog-mode to an emacs package repository (i.e. MELPA) ?
- 09:13 PM Verilog-mode Issue #635 (Closed): UVM-Component
Developing testbenches in the UVM, new object and component declarations are quite verbose. I have added to y...
- 11:43 AM Verilog-mode Issue #440 (Closed): Feature request: Verilog header - automatic update of the field 'Last Modifi...
- The verilog-mode provides a template of a header. Would it be possible to add an automatic update of the field 'Last ...
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