Veripool

02/28/2017

11:04 AM Verilator Issue #1131 (Closed): Internal error: InitArray on non-array

Got internal error ...

07/12/2016

09:50 AM Verilator Issue #1073: how to ignore the warning?

Short answer: you can't.
Long answer: Verilator simulates synthesizable verilog code and @#10@ is not synthesizabl...

07:20 AM Verilator Issue #1073: how to ignore the warning?

Generally two ways to disable warning.
You can add some comments in the verilog source where the warning is report...

03/07/2016

08:32 AM Verilator Issue #1044: Internal error when doing V3Simulate on for loop inside for loop

We have something like this ...

03/04/2016

03:13 PM Verilator Issue #1044 (Closed): Internal error when doing V3Simulate on for loop inside for loop

...

09/22/2015

01:24 PM Verilator Issue #966: Symbol table scope map

Wilson, nice that you like this debugging functionality. I definitely like this to be merged into the mainstream. Wil...

07:38 AM Verilator Development: RE: Problem while trying to use generate with for statement

If you change the line ...

09/18/2015

12:32 PM Verilator Usage: RE: Verilator signal reflection?

You can find the patch here in https://github.com/jiexu/verilator.git vardbg branch.
Answers to your questions:
...

12:23 PM Verilator Usage: RE: Problem with reset?

Glad you got it sorted out.
AFAIK, Verilator has no issue with supporting multicore cpu.

09/16/2015

07:18 AM Verilator Usage: RE: Problem with reset?

It is not wrong for Verilator to use vector clocks. The thing is that it is a lot harder for Verilator to decide the ...