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Corey Teffetalor

  • Email: Must_Login
  • Registered on: 03/27/2012
  • Last connection: 01/26/2019

Issues

Activity

01/28/2019

10:18 PM Verilog-Perl Issue #1394: Verilog::Std::std can return blank `std` package.
Confirmed, thanks for the quick fix!

01/26/2019

12:44 AM Verilog-Perl Issue #1394 (Closed): Verilog::Std::std can return blank `std` package.
Due to how perl `fork` behaves, @Verilog::Std::std@ can return no SystemVerilog std package definition. Additionally ...

03/17/2015

07:44 PM Verilog-Perl Issue #899: Lexing of `protected/`endprotected sections can never complete
Apologies, this was intended to be filed against Verilog::Perl, not Verilator. I can refile there if necessary.
06:22 PM Verilog-Perl Issue #899 (Closed): Lexing of `protected/`endprotected sections can never complete
`protected `endprotected sections are supported by a text callback in the Parser, however these may be VERY large in ...

04/09/2012

07:05 PM Verilog-Perl Issue #471: Parameters outside modules not recognized
Glanced at the git code. Thanks for the quick fix! Should be a good solution to retrieving these parameters.

03/27/2012

05:43 PM Verilog-Perl Issue #471 (Closed): Parameters outside modules not recognized
It seems that "parameter" statements outside of module scope are not recognized by the Verilog-Perl Verilog::Netlist ...

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