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Art. FR

  • Email: Must_Login
  • Registered on: 08/17/2012
  • Last connection: 03/02/2019

Issues

Activity

03/02/2019

10:53 AM Verilator Development: detecting edges in an initial block
Dear developers,
I was wondering if you could support the execution of the following code (which is supported by c...

03/18/2017

10:29 AM Verilator Usage: RE: empty vcd file
problem solved! Thanks Wilson.

03/16/2017

09:24 PM Verilator Usage: empty vcd file
Hello,
can anyone spot what's wrong with my example. The simulation produces good printf results but the VCD file is...

05/07/2014

02:04 PM Verilator Usage: RE: wreal usage
hello,
in order to model my analog functions I make extensive usage of delays (for settling times) and as long as ...

04/07/2014

02:50 PM Verilator Usage: Integrate Verilated code into HDL simulation using DPI
All,
I would like to validate my verilated RTL code using my existing HDL testbench in a commercial simulator.
...

07/26/2013

12:44 PM Verilator Usage: wreal usage
Hello everyone,
do I need any special options to verilate verilog-ams files with wreal?
here's the module I am ...

07/13/2013

02:43 PM Verilator Installation: RE: error with bison version 1.875
I tried this:
/pkg/fs-foundation-/dynamic/bin/bison -d -v -b ./src/obj_dbg/V3ParseBison_pretmp.y -o V3ParseBison_pre...
02:17 PM Verilator Installation: RE: error with bison version 1.875
Thanks for the quick reply Wilson!
please find below the full error message.
Here what bison says if asked for it...
11:19 AM Verilator Installation: error with bison version 1.875
All,
anyone figured out this issue?
bisonpre: %Error: /pkg/fs-foundation-/dynamic/bin/bison version 1.875 ru...

01/09/2013

04:24 PM Verilator Development: RE: Support for event driven subset of VerilogAMS (Wreal)
Thanks!
Today’s SoCs comprise an ever-increasing number of analog IPs. It wouldn't be bad to have AMS support.
...

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