- Email: Must_Login
- Registered on: 08/17/2012
- Last connection: 03/02/2019
- Dear developers,
I was wondering if you could support the execution of the following code (which is supported by c...
- 10:29 AM Verilator Usage: RE: empty vcd file
- problem solved! Thanks Wilson.
can anyone spot what's wrong with my example. The simulation produces good printf results but the VCD file is...
- 02:04 PM Verilator Usage: RE: wreal usage
in order to model my analog functions I make extensive usage of delays (for settling times) and as long as ...
I would like to validate my verilated RTL code using my existing HDL testbench in a commercial simulator.
- Hello everyone,
do I need any special options to verilate verilog-ams files with wreal?
here's the module I am ...
- 02:43 PM Verilator Installation: RE: error with bison version 1.875
- I tried this:
/pkg/fs-foundation-/dynamic/bin/bison -d -v -b ./src/obj_dbg/V3ParseBison_pretmp.y -o V3ParseBison_pre...
- 02:17 PM Verilator Installation: RE: error with bison version 1.875
- Thanks for the quick reply Wilson!
please find below the full error message.
Here what bison says if asked for it...
anyone figured out this issue?
bisonpre: %Error: /pkg/fs-foundation-/dynamic/bin/bison version 1.875 ru...
- 04:24 PM Verilator Development: RE: Support for event driven subset of VerilogAMS (Wreal)
Todayâ€™s SoCs comprise an ever-increasing number of analog IPs. It wouldn't be bad to have AMS support.
Also available in: Atom