- Email: Must_Login
- Registered on: 10/08/2012
- Last connection: 11/13/2019
- 02:23 AM Verilator Usage: RE: Very basic eval() usage question
- The code snippet I pasted above actually works fine. There was something in my actual app which didn't work, for some...
- I want to write some functions in the same C++ file as the main() function is in which will also call top->eval();
I've come across an issue where Verilator doesn't like clearing packed arrays. Eg:...
- 09:50 AM Verilator Issue #566 (Closed): Referencing SystemVerilog struct field of a member of an array of structs
- The following code throws an error like it's a hierarchical reference, however it's just accessing a field of a struc...
- I'd like to get a clarification for the reason for the following error:
Unsupported: Non-constant inside 's in ...
- 04:11 PM Verilator Issue #517: Constant expression in generated block index not recognized
- I am also wondering if there is an update on this feature.
I'm more interested in the case of addressing members i...
- 11:23 AM Verilator Usage: RE: Parameter in package used for signal width
- Whoops, I see the problem with what I was doing just now - not supposed to import the package inside the module!
- 11:20 AM Verilator Usage: RE: Parameter in package used for signal width
- Thanks Wilson, appreciated!
How are you importing the package? I can't seem to make it work.
If I try:
- 10:55 AM Verilator Usage: RE: Parameter in package used for signal width
- This actually appears to be an issue with fishing parameters out of packages in general:
If testcase.sv is simply:...
- If I have a SystemVerilog package declaring a parameter, and then attempt to use that parameter to define the width o...
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