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Austin Harris

  • Email: Must_Login
  • Registered on: 02/12/2013
  • Last connection: 10/16/2015

Issues

Activity

07/03/2013

06:38 PM Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd

Hello, the constraints indenting is working great now in most cases, however I am seeing an issue with the followin...

02/21/2013

07:45 AM Verilog-mode Issue #433: indenting for some forms of SystemVerilog constraints is wrong/odd
Can you please assign someone to fix this? Any OVM/UVM verification code is extremely annoying to deal with because o...

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