Veripool

12/15/2011

06:50 PM Verilog-mode Issue #104 (Resolved): Indentation failures in v528

I addressed this somewhat in version 736 (published 12/10/11 ) of the mode; the input/outputs are mutually aligned, b...

06:47 PM Verilog-mode Issue #290 (Resolved): Indentation wrong after import "DPI-C"

Fixed in release 736 (released 12/10/11)

06:46 PM Verilog-mode Issue #399 (Resolved): alignment of assignment operators and comparison operators

Fixed in release 736 (released 12/10/11)

02/21/2011

06:46 AM Verilog-mode Issue #260 (Closed): Feature Request: Autoformat/indent Verilog 2001 Module Headers

06:46 AM Verilog-mode Issue #260 (Resolved): Feature Request: Autoformat/indent Verilog 2001 Module Headers

Fixed with version 666 (oooh!) declarations are lined up inside modern style port declaration blocks.

02:21 AM Verilog-mode Issue #308: Indenting/Highlighting user defined types

Hmm, this is way difficult. I like Wilson's idea of using verilog-typedef-regexp as the single way to tell emacs how...

08/18/2010

11:40 PM Verilog-mode Issue #258 (Closed): "task automatic foo()" results in endcomment name "automatic"

Fixed in revision 636

06/03/2010

12:40 AM Verilog-mode Issue #218 (Closed): pure virtual indentation

Fixed with version 621

04/11/2010

01:03 AM Verilog-mode Issue #218 (Assigned): pure virtual indentation

It seems this is IEEE 1800-2009 syntax? I am getting a copy of the manual...

04/10/2010

10:57 PM Verilog-mode Issue #203 (Closed): Verilog-mode support for the `elsif directive

Thanks, Shankar Giri!