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Sean Moore

  • Email: Must_Login
  • Registered on: 06/24/2013
  • Last connection: 06/24/2013

Issues

Activity

06/24/2013

01:54 AM Verilator Issue #659 (Closed): Support finitely recursive modules
I'm getting an error thrown when trying to create recursively instantiated modules in Verilog.
@-Info-Loop: 0x92f9...

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