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David Rogoff

  • Email: Must_Login
  • Registered on: 04/05/2009
  • Last connection: 08/21/2019

Issues

Activity

07/23/2019

01:05 AM Verilog-mode Issue #386: Indenting of user-defined data types
Hi Wilson.
I'm hitting this again and my elisp still isn't good enough to fix this correctly. However, I've hacked...

07/15/2019

07:07 PM Verilog-mode Issue #1313: AUTOINST problem for module containing clocking block
Hi Wilson.
I just hit this problem again and wondered if there's been any activity on it during the past year.
...

06/21/2019

09:43 PM Verilog-mode Issue #1471: Describe how to find source file to debug autos
Thanks - that should do the trick!
08:47 PM Verilog-mode Issue #1471 (Closed): Describe how to find source file to debug autos
Hi.
Reading Issue #1464 reminded me of a debug feature that would be great. verilog-auto-inst-template-numbers is...

06/02/2019

06:05 PM Verilog-mode Issue #1453 (WillNotFix): Question: AUTOLOGIC/AUTOINST for unpacked array signal input to submodule
Hi Wilson.
Thanks for the super-quick answer to my last question!
Here's another:
I have a signal like this:...

06/01/2019

12:32 AM Verilog-mode Issue #1452 (NoFixNeeded): Use AUTO_TEMPLATE number from instance name to control string in port ...
Hi.
I'm using something like this to use the instance name to select the correct signal index for multiple instanc...

05/10/2019

01:06 AM Verilog-mode Issue #1257: Indentation within generate construct after always block is wrong if generate/endgen...
Even stranger - If I just put...
01:04 AM Verilog-mode Issue #1257: Indentation within generate construct after always block is wrong if generate/endgen...
I just hit this. What's really weird is if I have the same generate loop twice but have another one in the middle wi...

04/09/2019

08:17 PM Verilog-mode Issue #1416: problems getting Verilog-batch-auto to work with library file
Wilson Snyder wrote:
> -l path/to/verilog-mode.el
Ack - now it works. It looks like the whole problem was the an...
08:01 PM Verilog-mode Issue #1416: problems getting Verilog-batch-auto to work with library file
Wilson Snyder wrote:
> I would suggest adding an appropriate debug message near line 10130 where that error is print...

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