Veripool

08/12/2019

08:17 PM Verilator Issue #1487 (Resolved): New WIDTH warnings on genvars

Squashed, pushed and CI is green.
Verilator_ext_tests is working too. That CI environment is still a WIP, but is ...

01:14 PM Verilator Issue #1487: New WIDTH warnings on genvars

Here is my proposed fix:
https://github.com/toddstrader/verilator-dev/tree/genvar-width
It appears the specific i...

08/09/2019

10:06 PM Verilator Issue #1487: New WIDTH warnings on genvars

Re: t_lint_width_genfor, I'm thinking the WIDTH warning in the procedural block "ri = i;" may not really be new. I w...

07:38 PM Verilator Development: RE: RFC: DPI encapsulated Verilog instead of encryption

> That is, the generation of a protected model is NOT elaborating and compiling to a representation that supports dif...

08/08/2019

12:33 PM Verilator Development: RE: RFC: DPI encapsulated Verilog instead of encryption

> Can you describe why this is needed
For example, Xilinx provides the simulation model of its DSP as encrypted Veri...

08/07/2019

11:04 AM Verilator Development: RFC: DPI encapsulated Verilog instead of encryption

Please see:
https://github.com/toddstrader/dpi-compile
Any comments are welcomed, but I'd specifically like to as...

07/26/2019

10:16 PM Verilator Issue #1483 (Assigned): Make verilator_ext_tests head-to-head

This is still a WIP, but I think it warrants some discussion before I trudge ahead much further:
https://github.com/...

05:30 PM Verilator Issue #1305: Error messages do not contain hierarchical information

Sold. This has been squashed, pushed and is green.

03:51 PM Verilator Issue #1305: Error messages do not contain hierarchical information

I updated the branch with all these changes:
https://github.com/toddstrader/verilator-dev/tree/mod_stack_trace_10
...

09:22 AM Verilator Issue #1481: Add rr support to the perl wrappers

Squashed, pushed and green.
Can you explain the number of stars for each entry in Changes? It appears that they a...