- Email: Must_Login
- Registered on: 06/02/2014
- Last connection: 07/06/2019
- Verilator (Developer, 08/09/2019)
- 08:17 PM Verilator Issue #1487 (Resolved): New WIDTH warnings on genvars
- Squashed, pushed and CI is green.
Verilator_ext_tests is working too. That CI environment is still a WIP, but is ...
- 01:14 PM Verilator Issue #1487: New WIDTH warnings on genvars
- Here is my proposed fix:
It appears the specific i...
- 10:06 PM Verilator Issue #1487: New WIDTH warnings on genvars
- Re: t_lint_width_genfor, I'm thinking the WIDTH warning in the procedural block "ri = i;" may not really be new. I w...
- 07:38 PM Verilator Development: RE: RFC: DPI encapsulated Verilog instead of encryption
- > That is, the generation of a protected model is NOT elaborating and compiling to a representation that supports dif...
- 12:33 PM Verilator Development: RE: RFC: DPI encapsulated Verilog instead of encryption
- > Can you describe why this is needed
For example, Xilinx provides the simulation model of its DSP as encrypted Veri...
- Please see:
Any comments are welcomed, but I'd specifically like to as...
- 10:16 PM Verilator Issue #1483 (Assigned): Make verilator_ext_tests head-to-head
- This is still a WIP, but I think it warrants some discussion before I trudge ahead much further:
- 05:30 PM Verilator Issue #1305: Error messages do not contain hierarchical information
- Sold. This has been squashed, pushed and is green.
- 03:51 PM Verilator Issue #1305: Error messages do not contain hierarchical information
- I updated the branch with all these changes:
- 09:22 AM Verilator Issue #1481: Add rr support to the perl wrappers
- Squashed, pushed and green.
Can you explain the number of stars for each entry in Changes? It appears that they a...
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