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L JEPSON

  • Email: Must_Login
  • Registered on: 06/17/2014
  • Last connection: 06/17/2014

Issues

Activity

07/01/2014

04:45 PM Verilog-mode General: RE: auto-indent messes up when 'class' used as other than SV keyword
If you do have a chance to address this, another area where verilog-mode might be changed is when I forward typedef a...

06/20/2014

04:44 PM Verilog-mode General: RE: auto-indent messes up when 'class' used as other than SV keyword
In posting this example code, I retyped the issue as a simpler example w/o compiling/simulating it. In doing so, I ...

06/17/2014

11:57 PM Verilog-mode General: auto-indent messes up when 'class' used as other than SV keyword
...

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