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Introduction to VCS Force-Gate Simulation Utilities

Written by Duane Galbi.

Summary

Utilities to run VCS simulations where are forcing specific nodes during the simulations. This is useful for gate-level power simulations, as well as other gate-level simulations.

Included utilites and basic usage

1) filter_vcd

A general utility for working with VCD files. It has the ability to use a <map-file> to extract data from a VCD and create input files for "force_reg.c".


<map-file> line format: <vcd-name> [INV=1] <vcs-name> [DLY=<int>]


Example: filter_vcd <input-vcd> -slist <map-file> -freg <name>

Creates <name>.names_txt and <name>.data_txt for force_reg.c PLI


2) force_reg.c

A PLI routine which allows one to force specific nodes during a VCS simulation

Example verilog code: (assumes filter_vcd with "-freg test -freg_evar eflag")

initial begin
  eflag = 0;
  $force_reg("test.names_txt","test.data_txt",`DUT_INST,"G");
end
always @(posedge eflag) $finish;

Compile: vcs <verilog-files> -full64 +vpi force_reg.c -P force_reg.tab +cli+4

See also

Measuring Active Power Using PrimeTime PX (PT PX): A User Perspective [Paper] - Using PrimeTime PX (PT PX) to measure active power, including conditions under which the generated power numbers are inaccurate and strategies to avoid these pitfalls. Presented to SNUG Boston 2010 by Duane E. Galbi, Karthik Kannan.