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Introduction to Verilator


Welcome to Verilator.

Verilator is the fastest free Verilog HDL simulator, and outperforms most commercial simulators. Verilator compiles synthesizable SystemVerilog (generally not test-bench code), plus some SystemVerilog and Synthesis assertions into single- or multithreaded C++ or SystemC code. Verilator was designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Verilator is being used to simulate many very large multi-million gate designs with thousands of modules, and is supported by many IP vendors out-of-the box, including IP from Arm and all known RISC-V IP vendors. Verilator is a project guided by the CHIPS Alliance and Linux Foundation.

Verilator may not be the best choice if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator, or a behavioral Verilog simulator for a quick class project (we recommend Icarus Verilog instead.) However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and your team is comfortable writing just a touch of C++ code, this is the free Verilog compiler for you.

Give Verilator a try, and if you wish, contribute back to its development.


Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather than only translate, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a single-thread over 10x faster than standalone SystemC, and on a single thread is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). Verilator has typically similar or slightly better performance as the commercial Verilog simulators (Carbon Design Systems Carbonator, Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is free, so you can spend on computes rather than licenses. Thus Verilator gives you more cycles/dollar than anything else available.

If you benchmark Verilator, please see the notes in the Verilator Manual and also if possible post on the forums the results; there may be additional tweaks possible.

Here's how Verilator in single-threaded mode stacks up to some of the other commercial and free Verilog simulators: Verilog Simulator Benchmarks

See Also

Other Notable Open-Source Simulators

There are three other notable open source simulators. Hopefully if Verilator does not suit your needs one of the others may:

  • Icarus Verilog - Icarus is a full featured interpreted Verilog 1995 simulator, with VHDL under development. Recommended.
  • Verilog2Cpp - Compiled simulator no longer supported (to our knowledge).
  • VBS - Verilog Behavioral Simulator no longer supported (to our knowledge).