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Introduction to Verilator

Written by Wilson Snyder <>, with John Coiner, Duane Galbi and Paul Wasson <>.


Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

Please do not download this program if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator or Verilog compiler for a little project! (Try Icarus instead.) However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and writing just a touch of C code and Makefiles doesn't scare you off, this is the free Verilog compiler for you.

Verilator supports the synthesis subset of Verilog, plus initial statements, proper blocking/non-blocking assignments, functions, tasks, multi-dimensional arrays, and signed numbers. It also supports very simple forms of SystemVerilog assertions and coverage analysis. Verilator supports the more important Verilog 2005 constructs, and some SystemVerilog features, with additional constructs being added as users request them.

Verilator has been used to simulate many very large multi-million gate designs with thousands of modules.


Verilator does not simply convert Verilog HDL to C++ or SystemC. Direct translation alone is fairly easy (and was what Verilator abandoned over 5 years ago). Rather than translate, Verilator compiles your code into a much faster optimized model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes over 10x faster than standalone SystemC.

Verilator is about 100 times faster than interpreted Verilog simulators such as Icarus Verilog. Verilator has about the same performance as the leading commercial Verilog simulators including Carbon Design Systems Carbonator, Modelsim, Cadence NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC, but is free, so you can spend on computes rather than licenses. Thus Verilator gives you more cycles/dollar than anything else available. (If you benchmark Verilator, please see the notes in the Verilator Manual and also let the author know the results; there may be additional tweaks possible.)

Here's how Verilator stacks up to some of the other commercial and free Verilog simulators:

Verilog Simulator Benchmarks

See Also

Verilator Installation

Verilator Documentation

Verilator FAQ

Verilator Mailing Lists

Other Notable Open-Source Simulators

There are three other notable open source simulators. Hopefully if Verilator does not suit your needs one of the others may.

Icarus Verilog - Icarus is a full featured interpreted Verilog 1995 simulator, with VHDL under development. Recommended.

Verilog2Cpp - Compiled simulator no longer supported (to our knowledge)

VBS - Verilog Behavioral Simulator no longer supported (to our knowledge)